The present invention is directed to semiconductor devices and, more specifically, to thyristor-based semiconductor devices, such as thyristor-based memory devices and other thyristor-based current-switching circuits.
Recent technological advances in the semiconductor industry have permitted dramatic increases in integrated circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Presently, single-die microprocessors are being manufactured with many millions of transistors, operating at speeds of hundreds of millions of instructions per second and being packaged in relatively small, air-cooled semiconductor device packages. The improvements in such devices have led to a dramatic increase in their use in a variety of applications. As the use of these devices has become more prevalent, the demand for reliable and affordable semiconductor devices has also increased. Accordingly, the need to manufacture such devices in an efficient and reliable manner has become increasingly important.
An important part in the design, construction, and manufacture of semiconductor devices concerns semiconductor memory and other circuitry used to store information. Conventional random access memory devices include a variety of circuits, such as SRAM and DRAM circuits. The construction and formation of such memory circuitry typically involves forming at least one storage element and circuitry designed to access the stored information. DRAM is very common due to its high density (e.g., high density has benefits including low price), with DRAM cell size being typically between 6 F2 and 8 F2, where F is the minimum feature size. However, with typical DRAM access times of approximately 50 nSec, DRAM is relatively slow compared to typical microprocessor speeds and requires refresh. SRAM is another common semiconductor memory that is much faster than DRAM and, in some instances, is of an order of magnitude faster than DRAM. Also, unlike DRAM, SRAM does not require refresh. SRAM cells are typically constructed using 4 transistors and 2 resistors or 6 transistors, which result in much lower density and is typically between about 60 F2 and 100 F2.
Various SRAM cell designs based on a NDR (Negative Differential Resistance) construction have been introduced, ranging from a simple bipolar transistor to complicated quantum-effect devices. These cell designs usually consist of at least two active elements, including an NDR device. In view of size considerations, the construction of the NDR device is important to the overall performance of this type of SRAM cell. One advantage of the NDR-based cell is the potential of having a cell area smaller than four-transistor and six-transistor SRAM cells because of the smaller number of active devices and interconnections.
Conventional NDR-based SRAM cells, however, have many problems that have prohibited their use in commercial SRAM products. These problems include, among others: high standby power consumption due to the large current needed in one or both of the stable states of the cell; excessively high or excessively low voltage levels needed for cell operation; stable states that are too sensitive to manufacturing variations and provide poor noise-margins; limitations in access speed due to slow switching from one state to the other; limitations in operability due to temperature, noise, voltage and/or light stability; and manufacturability and yield issues due to complicated fabrication processing.
A thin capacitively-coupled thyristor-type NDR device can be effective in overcoming many previously unresolved problems for thyristor-based applications. An important consideration in the design of the thin capacitively-coupled thyristor device involves designing the body of the thyristor sufficiently thin, so that the capacitive coupling between the control port and the thyristor base region can substantially modulate the potential of the base region. Another important consideration in semiconductor device design, including those employing thin capacitively coupled thyristor-type devices and memory implementations, includes forming devices in a very dense array. In order to achieve such a dense array, it is sometimes desirable to form trenches having a very high aspect ratio (the ratio of height to width of the opening of the trench). Portions of the devices must be electrically insulated from other circuitry, however, and commonly used insulative materials are difficult to implement when filling trenches having high aspect ratios (e.g., greater than 2:1).
Another important consideration in semiconductor device design, including designs employing thin capacitively-coupled thyristor-type devices, includes the inhibition of parasitic current leakage from the device. Such leakage may occur, for example, between portions of the thyristor and adjacent circuitry (e.g., doped substrate) in the semiconductor device. In particular, thyristor devices coupled in series with adjacent pass devices are susceptible to parasitic MOSFET current passing between portions of the thyristor and the pass device and/or between portions of the pass device and other circuitry. For example, parasitic current can pass between a source/drain region of the pass device and an emitter region of the thyristor via a well region in the substrate of the semiconductor device. The parasitic current passes when a voltage pulse applied to the control port of the thyristor for switching the thyristor between conductance states also undesirably switches the well region into a conducting state. The parasitic current affects the operation of the device and can cause operational errors that may alter the performance of devices in which the thin capacitively-coupled thyristor device is used.
These and other design considerations have presented challenges to efforts to implement such a thin capacitively-coupled thyristor in bulk substrate applications, and in particular to applications susceptible to parasitic current.
The present invention is directed to overcoming the above-mentioned challenges and others related to the types of devices and applications discussed above and in other memory cells. The present invention is exemplified in a number of implementations and applications, some of which are summarized below.
According to an example embodiment of the present invention, a semiconductor device includes a thyristor having portions adjacent to doped regions of a substrate that are susceptible to passing leakage current therebetween in response to the operation of the thyristor. The substrate includes first and second doped portions doped to the same polarity and separated by a channel region. The thyristor includes a control port and a body having a region in the substrate, the channel region being susceptible to leakage current between the two doped regions in response to a voltage pulse being applied to the control port for controlling current flow in the thyristor body region in the substrate. The voltage pulse is used, for example, for switching the thyristor between current-passing and current blocking states (e.g., causing of an outflow of minority carriers in the thyristor body via the coupling of voltage pulses for switching the thyristor into a blocking state). The thyristor body, the control port and the first and second doped portions are arranged for inhibiting parasitic current leakage between the first and second doped portions via the channel region when the voltage pulse is applied to the control port. With this approach, control of the state of the thyristor can be achieved while addressing difficulties associated with the formation of a conductive channel in adjacent portions of the substrate, such as those discussed above.
According to another example embodiment of the present invention, a semiconductor device includes a thyristor that exhibits inhibited parasitic leakage current. The semiconductor device includes a substrate having first and second adjacent substrate regions of opposite doping, a thyristor and a current pass device. The thyristor includes a control port adapted for capacitively coupling to a thyristor body and adapted to control current in the thyristor body, where at least one region of the thyristor body is contiguously adjacent to the second doped substrate region. A first side of the control port faces the thyristor body and a second side of the control port faces the first doped substrate region. The current pass device is coupled in series with the thyristor body and includes a doped portion adjacent to the control port and immediately adjacent to the first doped substrate region. The second doped substrate region is adjacent to the control port, immediately adjacent to the first doped region and is doped with the same polarity as the doped portion. The thyristor body, the control port and the current pass device are configured and arranged to inhibit parasitic current leakage from the thyristor, including leakage that can occur through the second doped substrate region from the thyristor body region contiguously adjacent to the second doped substrate region.
In another more particular example embodiment of the present invention, the semiconductor device includes a lined trench that includes at least a portion of the control port. The lined trench includes a lining material on the sides of the control port, and the control port is adapted for capacitively coupling to the thyristor body via the lining material. A portion of the lining material between the control port and the first doped substrate region is relatively thicker than a portion of the lining material between the control port and the thyristor body. The relatively thicker liner material is adapted to inhibit the control port from forming a conductive channel in the first doped substrate region between the doped portion of the pass device and the second doped substrate region.
In another example embodiment of the present invention, a memory array includes at least one memory cell having a thyristor-based device adapted to exhibit inhibited parasitic current leakage, such as the thyristor-based devices described above. A thyristor is coupled in series with a pass device, wherein a gate of the pass device is part of a first word line and a control port of the thyristor is part of a second word line. The thyristor includes a body having first and second end portions, each end portion having a base region electrically coupled to an emitter region, the end portions being electrically coupled at the base regions. A control port including a portion of the second word line is adapted for capacitively coupling to the base region at the first end portion. The pass device includes first and second source/drain regions separated by a channel in the first doped substrate region, the gate being over the channel. The first source/drain region of the pass device is electrically coupled to the first emitter region of the thyristor and the second source/drain region of the pass device is electrically coupled to a bit line. The second emitter of the thyristor is electrically coupled to a voltage line (e.g., for holding the second emitter at a reference voltage). The pass device is adapted to switch between a current blocking state and a conducting state in response to a voltage being applied to the first word line. Similarly, the thyristor is adapted to switch between a current blocking state and a conducting state in response to at least one voltage pulse being applied to the second word line. Data is stored as the state of the thyristor, with access to the stored state being via the pass device. The memory cell is configured and arranged to inhibit the formation of a conductive channel (e.g., in response to the second word line voltage) between the first source/drain region and the second emitter region via the first and second doped regions.